Invention Grant
- Patent Title: Storage system for improved efficiency of parity generation and minimized processor load
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Application No.: US16084916Application Date: 2016-09-16
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Publication No.: US10664193B2Publication Date: 2020-05-26
- Inventor: Kenta Shinozuka , Takahiko Takeda , Isamu Kurokawa , Sho Sawada
- Applicant: Hitachi, Ltd.
- Applicant Address: JP Tokyo
- Assignee: HITACHI, LTD.
- Current Assignee: HITACHI, LTD.
- Current Assignee Address: JP Tokyo
- Agency: Procopio, Cory, Hargreaves & Savitch LLP
- International Application: PCT/JP2016/077533 WO 20160916
- International Announcement: WO2018/051505 WO 20180322
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F11/10

Abstract:
A controller is configured to receive a write request from a host, and send an intermediate parity generation command corresponding to a specified address indicated by the write request to a first storage device in storage devices. The intermediate parity generation command instructs generation of an intermediate parity from new data at the specified address and old data that is updated to the new data. The intermediate parity generation command includes a first address in the memory area at which the new data is stored and a second address in the memory area for storing the intermediate parity. The first storage device is configured to receive the intermediate parity generation command, acquire the new data from the first address, generate the intermediate parity from the new data and the old data stored in the first storage device, and store the intermediate parity at the second address.
Public/Granted literature
- US20190087122A1 STORAGE SYSTEM Public/Granted day:2019-03-21
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