A memory device, as provided herein, may include an invalidation bit circuit and a cell array. In methods for controlling such memory devices, the invalidation bit circuit may receive an invalid control command from a memory controller to update the invalid bit data to one of first and second states different from each other, the invalidation bit circuit may receive a read control command from the memory controller and may provide an invalid signal when the invalid bit data is in the first state, the invalidation bit circuit may transmit a data request when the invalid bit data is in the second state, and the cell array may receive the data request and provide data.