A computer system implementing transactional memory. The computing system includes a plurality of Single Instruction Multiple Thread (SIMT) cores and a conflicting address table (CAT) for each core. The CAT stores word addresses for reads and writes correlated with flags indicating whether a corresponding word is written or read by a committing transaction. The CATs for the different SIMT cores are coupled together by an interconnect. A commit unit (CU) is coupled to the SIMT cores and is configured to validate transactions. The cores access its CAT to access a first address of data affected by a first transaction to be committed at the CU. The first address is compared to a second address affected by a second transaction. When the first address matches the second address, the core delays or prevents committing the first transaction at the CU by pausing the first transaction or aborting the first transaction.