Invention Grant
- Patent Title: Multiple core analysis mode for defect analysis
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Application No.: US15969273Application Date: 2018-05-02
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Publication No.: US10664370B2Publication Date: 2020-05-26
- Inventor: Kenji Shiozawa , Yoshihide Nakamura , Takuya Lee , Yutaka Nakadai , Tetsuya Kokubun , Hiroyuki Sasaki
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@63aff4bc
- Main IPC: G06F11/22
- IPC: G06F11/22 ; G06F11/16

Abstract:
Related semiconductor devices have a problem in which analysis processing with high defect reproducibility cannot be performed. According to an embodiment, a semiconductor device includes a first arithmetic core that executes a first program stored in a first code area using a first local memory area and a second arithmetic core that executes a second program stored in a second code area using a second local memory area. In an analysis mode, the semiconductor device performs first analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the first program and second analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the second program, and compares a plurality of arithmetic result data pieces acquired from the first and second analysis processing to thereby acquire analysis information used for defect analysis.
Public/Granted literature
- US20190004914A1 SEMICONDUCTOR DEVICE Public/Granted day:2019-01-03
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