An array of resistive processing units (RPUs) comprises a plurality of rows of RPUs and a plurality of columns of RPUs wherein each RPU comprises an AND gate configured to perform an AND operation of a first stochastic bit stream received from a first stochastic translator translating a number encoded from a neuron in a row and a second stochastic bit stream received from a second stochastic translator translating a number encoded from a neuron in a column. A first storage is configured to store a weight value of the RPU, and a second storage is configured to store an amount of change to the weight value of the RPU. When the first stochastic bit stream and the second stochastic bit stream coincide, the amount of change to the weight value of the RPU is added to the weight value of the RPU.