Invention Grant
- Patent Title: Spacer etching process for integrated circuit design
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Application No.: US15357203Application Date: 2016-11-21
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Publication No.: US10665467B2Publication Date: 2020-05-26
- Inventor: Ru-Gun Liu , Cheng-Hsiung Tsai , Chung-Ju Lee , Chih-Ming Lai , Chia-Ying Lee , Jyu-Horng Shieh , Ken-Hsien Hsieh , Ming-Feng Shieh , Shau-Lin Shue , Shih-Ming Chang , Tien-I Bao , Tsai-Sheng Gau
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L21/8234 ; H01L21/033 ; H01L21/311 ; H01L21/768 ; H01L21/02 ; H01L21/027 ; H01L21/3105

Abstract:
A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
Public/Granted literature
- US20170069505A1 Spacer Etching Process for Integrated Circuit Design Public/Granted day:2017-03-09
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