Invention Grant
- Patent Title: Semiconductor device with reduced via bridging risk
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Application No.: US16148071Application Date: 2018-10-01
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Publication No.: US10665506B2Publication Date: 2020-05-26
- Inventor: Szu-Wei Tseng , Kuo-Chiang Tsai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L27/11 ; H01L21/311

Abstract:
First and second gates and first and second conductive contacts are disposed over a substrate. First and second vias are disposed over the first and second conductive contacts, respectively. A first gate contact is disposed over the first gate. A dielectric structure is disposed over the first gate and over the second gate. A first portion of the dielectric structure is disposed between the first and second vias. A second portion of the dielectric structure is disposed between the first via and the first gate contact. A first interface between the first conductive contact and the first via constitutes a first percentage of an upper surface area of the first conductive contact. A second interface between the first gate and the first gate contact constitutes a second percentage of an upper surface area of the first gate. The first percentage is greater than the second percentage.
Public/Granted literature
- US20200006139A1 SEMICONDUCTOR DEVICE WITH REDUCED VIA BRIDGING RISK Public/Granted day:2020-01-02
Information query
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