Invention Grant
- Patent Title: Package structure and manufacturing method thereof
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Application No.: US15939292Application Date: 2018-03-29
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Publication No.: US10665537B2Publication Date: 2020-05-26
- Inventor: Chien-Ling Hwang , Chun-Lin Lu , Kai-Chiang Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/31 ; H01L23/66 ; H01L21/48 ; H01L21/56

Abstract:
A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.
Public/Granted literature
- US20190304901A1 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2019-10-03
Information query
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