Invention Grant
- Patent Title: Metal isolation testing in the context of memory cells
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Application No.: US15903770Application Date: 2018-02-23
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Publication No.: US10665595B2Publication Date: 2020-05-26
- Inventor: Te-Hsin Chiu , Meng-Han Lin , Wei Cheng Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L27/11 ; H01L23/528 ; G11C29/50 ; G11C29/08 ; G11C29/04 ; G11C29/12 ; G06F30/39 ; G06F30/398

Abstract:
In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.
Public/Granted literature
- US20190067300A1 METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS Public/Granted day:2019-02-28
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