Disclosed is a manufacturing method of an array substrate, comprising steps of: depositing a first metal layer on a substrate; depositing a gate insulating layer on the substrate and the first metal layer, and forming a first via hole in the in-plane region of the gate insulating layer; depositing a second metal layer in an in-plane region and an out-of-plane of the gate insulating layer, wherein the second metal layer located in the in-plane region fills the first via hole; depositing a passivation layer on the second metal layer and the gate insulating layer, and forming a second via hole in the in-plane region of the passivation layer; forming a third via hole and a fourth via hole in the out-of plane region of the passivation layer, respectively; depositing a transparent conductive layer in the in-plane region and in the out-of-plane region of the passivation layer, respectively.