Invention Grant
- Patent Title: Non-self aligned gate contacts formed over the active region of a transistor
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Application No.: US16169161Application Date: 2018-10-24
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Publication No.: US10665692B2Publication Date: 2020-05-26
- Inventor: Ruilong Xie , Chanro Park , Kangguo Cheng , Julien Frougier
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Joseph Petrokaitis
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/768 ; H01L29/78 ; H01L21/02 ; H01L21/8234 ; H01L21/3105

Abstract:
A method for forming a silicon structure. The method includes forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates. The method planarizes the trench silicide contact, the spacers, and the high-k metal gates. An inner layer dielectric is deposited over the trench silicide contact, the spacers, and the high-k metal gates. A first opening is patterned in the inner layer dielectric for a gate contact over the high-k metal gate, one of the spacers and a portion of the trench silicide contact. The method recesses the portion of the trench silicide contact and deposits a liner within the recessed portion of the trench silicide contact and on sidewalls of the first opening of the inner layer dielectric. A metallization layer is deposited in the opening in the inner layer dielectric to form the gate contact.
Public/Granted literature
- US20200135885A1 NON-SELF ALIGNED GATE CONTACTS FORMED OVER THE ACTIVE REGION OF A TRANSISTOR Public/Granted day:2020-04-30
Information query
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