Invention Grant
- Patent Title: Vertical transistors with various gate lengths
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Application No.: US16023535Application Date: 2018-06-29
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Publication No.: US10665714B2Publication Date: 2020-05-26
- Inventor: Juntao Li , Kangguo Cheng , ChoongHyun Lee , Shogo Mochizuki
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8234 ; H01L29/66 ; H01L27/088 ; H01L29/10

Abstract:
A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.
Public/Granted literature
- US20200006553A1 VERTICAL TRANSISTORS WITH VARIOUS GATE LENGTHS Public/Granted day:2020-01-02
Information query
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