Invention Grant
- Patent Title: Controlling gate length of vertical transistors
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Application No.: US16114613Application Date: 2018-08-28
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Publication No.: US10665715B2Publication Date: 2020-05-26
- Inventor: Praveen Joseph , Indira Seshadri , Ekmini A. De Silva , Stuart A. Sieg
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8234 ; H01L21/033 ; H01L21/02 ; H01L21/768 ; H01L29/66 ; H01L29/08

Abstract:
A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.
Public/Granted literature
- US20200075761A1 CONTROLLING GATE LENGTH OF VERTICAL TRANSISTORS Public/Granted day:2020-03-05
Information query
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