Invention Grant
- Patent Title: System and method for compacting X-pessimism fixes for gate-level logic simulation
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Application No.: US15798247Application Date: 2017-10-30
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Publication No.: US10666255B1Publication Date: 2020-05-26
- Inventor: Kai-Hui Chang , Hong-zu Chou
- Applicant: Avery Design Systems, Inc.
- Applicant Address: US MA Tewksbury
- Assignee: Avery Design Systems, Inc.
- Current Assignee: Avery Design Systems, Inc.
- Current Assignee Address: US MA Tewksbury
- Agency: Loginov & Associates, PLLC
- Agent William A. Loginov
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K19/003 ; H03K19/173 ; G06F30/33

Abstract:
A computer executable tool analyzes Boolean logic in a gate-level netlist responsible for generating false Xs due to X-pessimism in logic simulation to produce a compact fix that corrects the X-pessimism problem. The fix restores logic simulation value from X to hardware-accurate non-X value and solves X-pessimism issues in logic simulation.
Information query