Invention Grant
- Patent Title: 3D stacked integrated circuits having failure management
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Application No.: US16218889Application Date: 2018-12-13
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Publication No.: US10666264B1Publication Date: 2020-05-26
- Inventor: Tony M. Brewer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Greenberg Traurig
- Main IPC: H03K19/17756
- IPC: H03K19/17756 ; H01L27/11526 ; H03K17/687 ; H03K19/17704 ; H01L27/06 ; H01L27/24 ; H03K19/17764 ; H03K19/0948 ; G11C16/04

Abstract:
A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, and a logic die. The non-volatile memory die, the volatile memory die, and the logic die are stacked. The 3D SIC is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. Each column of the plurality of columns is configurable to be bypassed via configurable routes. When the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.
Information query
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