Invention Grant
- Patent Title: Mitigation of error correction failure due to trapping sets
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Application No.: US16225272Application Date: 2018-12-19
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Publication No.: US10666295B1Publication Date: 2020-05-26
- Inventor: Ludovic Danjean , Sundararajan Sankaranarayanan , Ivana Djurdjevic , AbdelHakim Alhussien , Erich F. Haratsch
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Fremont
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Fremont
- Agency: Setter Roche LLP
- Agent Kirk A Cesari
- Main IPC: H03M13/11
- IPC: H03M13/11 ; G06F11/10 ; H03M13/00

Abstract:
An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.
Information query
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