Invention Grant
- Patent Title: Layout for reduced cross-talk in common terminal transistor
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Application No.: US15947389Application Date: 2018-04-06
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Publication No.: US10670638B2Publication Date: 2020-06-02
- Inventor: Vijay Krishnamurthy , Abidur Rahman , Min Chu , Sualp Aras
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Tuenlap Chan; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R19/10
- IPC: G01R19/10 ; H01L29/78 ; G01R19/00 ; H03K17/16 ; H01L29/735 ; H01L27/088 ; H01L29/06 ; H01L21/8234

Abstract:
A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.
Public/Granted literature
- US20190137546A1 LAYOUT FOR REDUCED CROSS-TALK IN COMMON TERMINAL TRANSISTOR Public/Granted day:2019-05-09
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