Coding scheme for indirect addressing of multiple action memories
Abstract:
Some embodiments provide a method for configuring unit memories to implement first and second sets of entries, the second set of which references the first set. The method configures a first pool of unit memories to implement the first set. Each entry in the first set is located at a particular location in at least one of the memories of the first pool. The method configures a second pool of unit memories to implement the second set. Each entry in the second set includes a particular number of bits for indicating (i) an initial first-pool unit memory at which the first-set entry referenced by the second-set entry is found and (ii) a number of subsequent first-pool memories across which the first-set entry is divided. A number of bits required to identify a single first-pool memory is one fewer than the particular number of bits.
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