Invention Grant
- Patent Title: Circuit assignment within reconfigurable device based on predicted shortest processing completion time
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Application No.: US15708185Application Date: 2017-09-19
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Publication No.: US10671429B2Publication Date: 2020-06-02
- Inventor: Kentaro Katayama
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@52c195f9
- Main IPC: G06F9/48
- IPC: G06F9/48 ; G06F9/52 ; G06F15/78 ; G06F30/34 ; H03K19/17756 ; G06F9/50

Abstract:
An information processing apparatus includes: a reconfiguration device which can change a circuit configuration through a dynamic partial reconfiguration; and a controller which controls a circuit arrangement in the reconfiguration device, in which when a processing circuit related to a new task is arranged in the reconfiguration device, the controller determines a circuit assignment of a processing circuit related to an existing task in execution and the processing circuit related to the new task with respect to an area as a result of combining an area used for the processing circuit related to the existing task in execution and a space area, based on a predicted end time of the processing of the respective tasks, and arranges the processing circuits related to the respective tasks in the reconfiguration device in accordance with the determined circuit assignment.
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