A memory controller and a memory system including the same are provided. The memory controller includes a memory storing a flash translation layer (FTL) mapping table, which includes a physical page number (PPN) of a flash memory and a logical page number (LPN) corresponding to the PPN; a central processing unit (CPU) accessing a memory mapped address space to which a logical address corresponding to the LPN is allocated; and an LPN translator receiving the logical address from the CPU, extracting an LPN corresponding to the logical address, reading, from the memory, the FTL mapping table corresponding to the extracted LPN, extracting a PPN corresponding to the extracted LPN, and transmitting the extracted PPN to the CPU.