Invention Grant
- Patent Title: Systems and methods for reducing first level cache energy by eliminating cache address tags
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Application No.: US14549042Application Date: 2014-11-20
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Publication No.: US10671543B2Publication Date: 2020-06-02
- Inventor: Erik Hagersten , Andreas Sembrant , David Black-Schaffer , Stefanos Kaxiras
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-Do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Main IPC: G06F12/1045
- IPC: G06F12/1045 ; G06F12/0864 ; G06F12/0897

Abstract:
Methods and systems which, for example, reduce energy usage in cache memories are described. Cache location information regarding the location of cachelines which are stored in a tracked portion of a memory hierarchy is stored in a cache location table. Address tags are stored with corresponding location information in the cache location table to associate the address tag with the cacheline and its cache location information. When a cacheline is moved to a new location in the memory hierarchy, the cache location table is updated so that the cache location information indicates where the cacheline is located within the memory hierarchy.
Public/Granted literature
- US20150143046A1 SYSTEMS AND METHODS FOR REDUCING FIRST LEVEL CACHE ENERGY BY ELIMINATING CACHE ADDRESS TAGS Public/Granted day:2015-05-21
Information query
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