A system and method to perform an ordered write of timing analysis data obtained in parallel during integrated circuit development process two or more data sets with two or more processors in parallel. The two or more data sets result from timing analysis and correspond with two or more paths, each path includes a set of interconnected components, and the processing includes collecting and formatting information to obtain the timing analysis data associated with each of the two or more paths. The method includes determining a next timing analysis data using an ordered list of the two or more data sets that correspond with the timing analysis data, consulting an availability vector to determine whether the next timing analysis data is available, and writing the next timing analysis data as soon as it is available prior to completion of the processing of others of the two or more data sets.