Invention Grant
- Patent Title: Integrated circuit and layout method
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Application No.: US15655763Application Date: 2017-07-20
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Publication No.: US10671789B2Publication Date: 2020-06-02
- Inventor: Jack Liu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: G06F30/394
- IPC: G06F30/394 ; G06F30/392 ; H01L23/522 ; H01L23/528

Abstract:
A system includes at least one Input/Output (I/O) interface and a processor. The processor is coupled to the at least one I/O interface. The processor is configured to perform, according to a file or a rule inputted from the at least one I/O interface, operations below. When the at least one condition is present in a signal to be received or transmitted by a terminal of a cell, a plurality of conductive segments is assigned to the terminal of the cell, to transmit the signal to the terminal of the cell. When the at least one condition one is not present in the signal, a single route is assigned to the terminal of the cell, to transmit the signal to the terminal of the cell. The single route and each of the conductive segments are configured to have the same width.
Public/Granted literature
- US20170316144A1 INTEGRATED CIRCUIT AND LAYOUT METHOD Public/Granted day:2017-11-02
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