Invention Grant
- Patent Title: Method and apparatus for verifying structural correctness in retimed circuits
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Application No.: US15790009Application Date: 2017-10-22
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Publication No.: US10671790B2Publication Date: 2020-06-02
- Inventor: Mahesh A. Iyer
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/398
Abstract:
A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.
Public/Granted literature
- US20180039724A1 Method and Apparatus for Verifying Structural Correctness in Retimed Circuits Public/Granted day:2018-02-08
Information query
