Invention Grant
- Patent Title: Current mirror scheme for an integrating neuron circuit
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Application No.: US15047936Application Date: 2016-02-19
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Publication No.: US10671911B2Publication Date: 2020-06-02
- Inventor: Mark B. Ritter , Takeo Yasuda
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: G06N3/063
- IPC: G06N3/063 ; G05F3/26 ; G06N3/04 ; G06N3/08

Abstract:
Embodiments are directed to a driver circuit including a first amplifier having a voltage follower configured to control a first node to maintain a voltage of the first node at a constant value. By maintaining the first node voltage, the first amplifier having the voltage follower is further configured to have a first amplifier output current into the first node at a value without the effect of the voltage fluctuation. The driver circuit further includes a second amplifier configured to control a second node, wherein the second amplifier is in a current mirror configuration with respect to the first amplifier such that a second amplifier current output is a highly precise mirror of the first amplifier current output.
Public/Granted literature
- US20170243108A1 Current Mirror Scheme for An Integrating Neuron Circuit Public/Granted day:2017-08-24
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