Invention Grant
- Patent Title: Write cycle execution based on data comparison
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Application No.: US16572278Application Date: 2019-09-16
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Publication No.: US10672440B2Publication Date: 2020-06-02
- Inventor: Jeffrey Frederiksen
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C16/26 ; G11C16/10 ; G11C8/12 ; G06F12/0882

Abstract:
Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits. The processing device determines whether to execute a write cycle, at the first memory component, to write the first sequence of data bits from the first data block to the memory media of the first memory component based on a result of comparing the first sequence of data bits with the second sequence of data bits.
Public/Granted literature
- US20200058334A1 WRITE CYCLE EXECUTION BASED ON DATA COMPARISON Public/Granted day:2020-02-20
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