A data management circuit is provided. The data management circuit includes a volatile memory, a power supply circuit, and a signal receiving circuit. An output terminal of the power supply circuit is coupled to the volatile memory, and an output terminal of the signal receiving circuit is coupled to the output terminal of the power supply circuit and the volatile memory. The power supply circuit is configured to provide power to the volatile memory. The signal receiving circuit is configured to receive a wireless control signal and to output a data clearance signal corresponding to the wireless control signal, such that data recorded in the volatile memory is cleared by the data clearance signal.