Invention Grant
- Patent Title: Method of making fully molded peripheral package on package device
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Application No.: US16012678Application Date: 2018-06-19
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Publication No.: US10672624B2Publication Date: 2020-06-02
- Inventor: Christopher M. Scanlan , William Boyd Rogers , Craig Bishop
- Applicant: DECA Technologies Inc.
- Applicant Address: US AZ Tempe
- Assignee: Deca Technologies Inc.
- Current Assignee: Deca Technologies Inc.
- Current Assignee Address: US AZ Tempe
- Agency: Booth Udall Fuller, PLC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L23/538 ; H01L23/498 ; H01L21/768 ; H01L23/48 ; H01L21/78 ; H01L21/52 ; H01L23/31 ; H01L25/10 ; H01L21/304

Abstract:
A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer.
Public/Granted literature
- US20180330966A1 FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE Public/Granted day:2018-11-15
Information query
IPC分类: