Invention Grant
- Patent Title: Wafer level chip scale packaging intermediate structure apparatus and method
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Application No.: US16049499Application Date: 2018-07-30
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Publication No.: US10672647B2Publication Date: 2020-06-02
- Inventor: Chen-Hua Yu , Der-Chyang Yeh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/31 ; H01L23/00 ; H01L23/538 ; H01L21/56 ; H01L25/10 ; H05K3/42 ; H05K3/46 ; H01L23/498
Abstract:
Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.
Public/Granted literature
- US20180342414A1 Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method Public/Granted day:2018-11-29
Information query
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