Invention Grant
- Patent Title: Multi-layer molded substrate with graded CTE
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Application No.: US16061890Application Date: 2015-12-23
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Publication No.: US10672695B2Publication Date: 2020-06-02
- Inventor: Srinivas Pietambaram , Rahul N. Manepalli
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- International Application: PCT/US2015/000185 WO 20151223
- International Announcement: WO2017/111772 WO 20170629
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/373 ; H01L21/48 ; H01L23/28
Abstract:
This document discusses, among other things, a multi-layer molded substrate having layers with a graded coefficients of thermal expansions (CTEs) to optimize thermal performance of the multi-layer molded substrate with first and second structures attached to top and bottom surfaces of the multi-layer molded substrate, respectively.
Public/Granted literature
- US20180366399A1 MULTI-LAYER MOLDED SUBSTRATE WITH GRADED CTE Public/Granted day:2018-12-20
Information query
IPC分类:
