Invention Grant
- Patent Title: Semiconductor device
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Application No.: US15809697Application Date: 2017-11-10
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Publication No.: US10672725B2Publication Date: 2020-06-02
- Inventor: Kazuo Tomita
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@3cf7c7a
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L23/58 ; H01L23/522 ; H01L23/00 ; H01L23/528

Abstract:
The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Vias are formed in each layer on a dicing region side. The vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.
Public/Granted literature
- US20180166401A1 SEMICONDUCTOR DEVICE Public/Granted day:2018-06-14
Information query
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