Invention Grant
- Patent Title: Three-dimensional integrated circuit structure and method of manufacturing the same
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Application No.: US15874893Application Date: 2018-01-19
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Publication No.: US10672737B2Publication Date: 2020-06-02
- Inventor: Yi-Hsiu Chen , Ebin Liao , Hong-Ye Shih , Wen-Chih Chiou , Jia-Ling Ko
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/56 ; H01L25/00 ; H01L23/544 ; H01L21/822 ; H01L23/31
Abstract:
Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 μm.
Public/Granted literature
- US20190139935A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2019-05-09
Information query
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