Invention Grant
- Patent Title: Method of fabricating a transistor having a drain pad with capping and silicide layers
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Application No.: US15990271Application Date: 2018-05-25
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Publication No.: US10672769B2Publication Date: 2020-06-02
- Inventor: Chia-Hao Chang , Ming-Shan Shieh , Cheng-Long Chen , Wai-Yi Lien , Chih-Hao Wang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/78 ; H01L29/45 ; H01L29/417 ; H01L29/423 ; H01L21/8238 ; H01L21/285 ; H01L29/786 ; H01L29/06 ; H01L23/485 ; H01L21/768

Abstract:
A method includes forming a transistor over a substrate, wherein the transistor includes a source, a drain over the source, a semiconductor channel between the source and the drain, and a gate surrounding the semiconductor channel. A silicide layer is formed over the drain of the transistor. A capping layer is formed over the silicide layer. Portions of the capping layer and the silicide layer are removed to define a drain pad over the drain of the transistor.
Public/Granted literature
- US20180277538A1 METHOD OF FABRICATING INTEGRATED CIRCUIT Public/Granted day:2018-09-27
Information query
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