Invention Grant
- Patent Title: Semiconductor memory device having a multi-region semiconductor layer
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Application No.: US16117649Application Date: 2018-08-30
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Publication No.: US10672788B2Publication Date: 2020-06-02
- Inventor: Yuya Maeda , Hidenori Miyagawa
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@7c710a73
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L29/423 ; H01L29/66 ; H01L29/792 ; G11C16/04 ; G11C16/24 ; H01L27/11582

Abstract:
A semiconductor memory device includes conductive layers and insulation layers alternately stacked along a first direction. A core member extends through the insulation layers and conductive layers. A semiconductor layer on an outer periphery of the core member has a first region facing a conductive layer of the stack and a second region adjacent to the first region and facing an insulation layer. The first region has a first thickness and a first impurity concentration. The second region has a second thickness that is greater than the first thickness and a second impurity concentration that is different from the first impurity concentration. A charge accumulation film is between the semiconductor layer and the conductive layer in a second direction crossing the first direction.
Public/Granted literature
- US20190296039A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2019-09-26
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