Invention Grant
- Patent Title: Bulk semiconductor substrate configured to exhibit semiconductor-on-insulator behavior
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Application No.: US16118098Application Date: 2018-08-30
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Publication No.: US10672795B2Publication Date: 2020-06-02
- Inventor: Gulbagh Singh , Kun-Tsang Chuang , Hsin-Chi Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L27/01
- IPC: H01L27/01 ; H01L27/12 ; H01L29/10 ; H01L21/265 ; H01L21/84 ; H01L21/762 ; H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L29/786

Abstract:
Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.
Public/Granted literature
- US20200006386A1 Bulk Semiconductor Substrate Configured to Exhibit Semiconductor-on-Insulator Behavior Public/Granted day:2020-01-02
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