Invention Grant
- Patent Title: Multi-terminal inductor for integrated circuit
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Application No.: US16587305Application Date: 2019-09-30
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Publication No.: US10672860B2Publication Date: 2020-06-02
- Inventor: Ching-Chung Hsu , Chung-Long Chang , Tsung-Yu Yang , Hung-Chi Li , Cheng-Chieh Hsieh , Che-Yung Lin , Grace Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01F27/28 ; H01L23/00 ; H01F27/29 ; H01F27/24 ; H01L21/768 ; H05K1/18 ; H01L23/528 ; H01L23/522 ; H01L21/321 ; H01L21/027

Abstract:
A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.
Public/Granted literature
- US20200066831A1 MULTI-TERMINAL INDUCTOR FOR INTEGRATED CIRCUIT Public/Granted day:2020-02-27
Information query
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