Invention Grant
- Patent Title: Ferroelectric gate dielectric with scaled interfacial layer for steep sub-threshold slope field-effect transistor
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Application No.: US15608480Application Date: 2017-05-30
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Publication No.: US10672881B2Publication Date: 2020-06-02
- Inventor: Takashi Ando , Martin M. Frank , Vijay Narayanan
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L29/78 ; H01L29/66 ; H01L29/49

Abstract:
A method is presented for forming a semiconductor device. The method includes forming an oxygen containing interfacial layer on a semiconductor substrate, forming a hafnium oxide layer on the interfacial layer, the hafnium oxide layer crystallizing to a non-centrosymmetric phase in a final structure, forming a first electrode containing a scavenging metal, which reduces a thickness of the interfacial layer via an oxygen scavenging reaction in the final structure, on the hafnium oxide layer, and forming a second electrode on the first electrode.
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