Invention Grant
- Patent Title: Stacked gate all around MOSFET with symmetric inner spacer formed via sacrificial pure Si anchors
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Application No.: US16152022Application Date: 2018-10-04
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Publication No.: US10672891B2Publication Date: 2020-06-02
- Inventor: Pouya Hashemi , Takashi Ando , Choonghyun Lee , Jingyun Zhang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Yee & Associates, P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/08 ; H01L21/311 ; H01L29/78 ; H01L29/423 ; H01L21/3065

Abstract:
A method of forming a stacked gate all around MOSFET is provided. A stack of alternating layers of Si and SiGe are formed on a substrate. A number of holes are etched through the stack and Si anchors formed in the holes. The SiGe layers are removed. A number of dummy gates are formed on the substrate and a Low-K spacer material deposited around the dummy gates. A number of S/D recesses are etched through the Si layers, removing the Si anchors. The dummy gates and spacer material preserves sections of the Si layers during etching, forming stacks of Si channels. S/Ds are formed in the recesses. The dummy gates are then removed replaced with metal gate stacks.
Public/Granted literature
- US20200111888A1 Stacked Gate All Around MOSFET with Symmetric Inner Spacer Formed via Sacrificial Pure Si Anchors Public/Granted day:2020-04-09
Information query
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