A switching regulator control circuit, having: a slope circuit 3 for generating a slope voltage VSLP on the basis of a clock signal CLK of a prescribed frequency; an error amplifier 1 for generating an error signal Vc corresponding to the difference between a reference voltage VREF and a voltage VFB corresponding to the output voltage of a switching regulator; a comparator 4 for comparing the error signal Vc and the slope voltage VSLP; and an RS flip-flop 6 set on the basis of the clock signal CLK and reset by a signal outputted by the comparator 4. The timing at which the RS flip-flop 6 is set is delayed with respect to the timing at which the sloping of the slope voltage VSLP is started.