Invention Grant
- Patent Title: Time-to-digital converter in phase-locked loop
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Application No.: US15713410Application Date: 2017-09-22
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Publication No.: US10673445B2Publication Date: 2020-06-02
- Inventor: Shenghua Zhou , Ran Song
- Applicant: Huawei Technologies Co., Ltd.
- Applicant Address: CN Shenzhen
- Assignee: Huawei Technologies Co., Ltd.
- Current Assignee: Huawei Technologies Co., Ltd.
- Current Assignee Address: CN Shenzhen
- Agency: Slater Matsil, LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@2276ad3a
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/197 ; G04F10/00 ; H03L7/085 ; H03L7/081 ; H03L7/095

Abstract:
A time-to-digital converter includes a delay unit into which a first signal is input and a sampling unit into which a second signal is input. The delay unit includes a first delay chain, a second delay chain, and a third delay chain that are connected in series in sequence. The delay unit delays the first signal. The first delay chain includes at least one first delayer. The second delay chain includes at least three second delayers. The third delay chain includes a third delayer. The delay duration of the first delayer and the delay duration of the third delayer are greater than delay duration of the second delayer. The sampling unit samples output signals of first delayers in the first delay chain, second delayers in the second delay chain, and third delayers in the third delay chain at a preset time point of the second signal.
Public/Granted literature
- US20180013437A1 TIME-TO-DIGITAL CONVERTER IN PHASE-LOCKED LOOP Public/Granted day:2018-01-11
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