Invention Grant
- Patent Title: Hybrid scheduling and latch-based pipelines for low-density parity-check decoding
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Application No.: US15778239Application Date: 2015-12-24
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Publication No.: US10673461B2Publication Date: 2020-06-02
- Inventor: Chia-Hsiang Chen , Wei Tang , Farhana Sheikh
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Viering, Jentschura & Partner MBB
- International Application: PCT/US2015/000424 WO 20151224
- International Announcement: WO2017/111853 WO 20170629
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/11 ; H04L1/18

Abstract:
A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.
Public/Granted literature
- US20180351575A1 HYBRID SCHEDULING AND LATCH-BASED PIPELINES FOR LOW-DENSITY PARITY-CHECK DECODING Public/Granted day:2018-12-06
Information query
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