Invention Grant
- Patent Title: Memory controller, memory system, and control method
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Application No.: US15693585Application Date: 2017-09-01
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Publication No.: US10673465B2Publication Date: 2020-06-02
- Inventor: Daiki Watanabe
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H03M13/39
- IPC: H03M13/39 ; G06F11/10 ; H03M13/15 ; H03M13/00 ; H03M13/45 ; H03M5/00 ; G11C29/52 ; G11C29/04 ; G11C29/10

Abstract:
A memory controller according to an embodiment includes a memory interface that reads out a received word from a non-volatile memory and a decoder that performs bounded distance decoding for the read received word. The decoder sets rm (rm is a natural number equal to or larger than 1) symbols of a plurality of symbols constituting the received word, as options of symbol positions at each of which an error is assumed, generates a test pattern in which m (m is a natural number equal to or larger than 1 and equal to or smaller than the rm) symbols of the rm symbols are objects of rewriting, generates test hard-decision values by rewriting each of hard-decision values of the m symbols that are objects of rewriting in the test pattern, among the symbols, and performs bounded distance decoding for the test hard-decision values.
Public/Granted literature
- US20180152207A1 MEMORY CONTROLLER, MEMORY SYSTEM, AND CONTROL METHOD Public/Granted day:2018-05-31
Information query
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