High-speed full-duplex transceiver and method thereof
Abstract:
A transceiver includes a first digital-to-analog converter (DAC) configured to receive a first digital code and output a first current to a first node; a second DAC configured to receive a second digital code and output a second current to a second node; first and second shunt resistors configured to shunt the first node and second nodes to a DC (direct current) node; a first DC coupling resistor coupling the first node to a third node; a second DC coupling resistor coupling the second node to the third node; an AC (alternate current) coupling capacitor coupling the third node to a fourth node; a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node; an inductive load configured to shunt the fifth node to a DC node; and an analog-to-digital conversion unit configured to receive a voltage at the fifth node and output a third digital code.
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