Invention Grant
- Patent Title: Semiconductor device and test method for semiconductor device
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Application No.: US15954665Application Date: 2018-04-17
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Publication No.: US10677844B2Publication Date: 2020-06-09
- Inventor: Iwao Suzuki , Naoki Kato
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@2c6773cf
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G01R31/3177 ; G06F11/22 ; G11C29/38 ; G01R31/317 ; G11C29/32
Abstract:
A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to a an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode.
Public/Granted literature
- US20180313894A1 SEMICONDUCTOR DEVICE AND TEST METHOD FOR SEMICONDUCTOR DEVICE Public/Granted day:2018-11-01
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