A digital state device may include a first circuit terminal that obtains a clock signal from a first integrated circuit. The digital state device may further include a second circuit terminal that transmits the clock signal to a second integrated circuit. The digital state device may further include digital logic circuitry coupled to the first circuit terminal and the second circuit terminal. In response to obtaining an in-band notification signal in reverse of the clock signal and from the second integrated circuit, the digital logic circuitry sets the clock signal to a first predetermined value. In response to the digital logic circuitry determining that the clock signal exceeds a predetermined amount of time at the first predetermined value, the digital logic circuitry sets the clock signal to a second predetermined value that is different from the first predetermined value.