The disclosure relates to a watchdog for monitoring a processor. The watchdog sends messages to the processor which subsequently sends back its own status information and optionally the status information of system components and the test results thereof at predetermined times as answers to the watchdog. The watchdog comprises at least one result memory in the form of, e.g., a shift register in which the watchdog records the history of the answers and examines patterns in erroneous answers. The recording is generated by a trigger event which can be the reception of individual answers and/or the end of scheduled reception time periods. According to the patterns, signalizations are carried out on the processor and/or other system components, which optionally introduce measures and adapt their structure and/or the implemented programs and/or the priority of said implementations.