Invention Grant
- Patent Title: Methods for performing Boolean operations on planar region boundaries defined by parametric curves
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Application No.: US16165973Application Date: 2018-10-19
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Publication No.: US10678986B1Publication Date: 2020-06-09
- Inventor: Janez Jaklic
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F30/39 ; G03F1/26 ; G06T11/20

Abstract:
A method includes receiving a first list including a plurality of first curves defining a first boundary set and a second list including a plurality of second curves defining a second boundary set. The first and second curves are indicative of features in an integrated circuit based on parametric values. The method includes determining intersections between pairs of curves from the first and the second lists, assigning a node to each intersection point of a pair of curves, and determining curve sections between the intersection points for each intersected curve. The method includes determining a successor of each curve section, determining boundaries formed by the curve sections, performing the Boolean operation between the boundaries to obtain the one or more features in the integrated circuit from the two or more boundaries, and generating a layout of the integrated circuit including the features for manufacturing a mask for reproducing the features.
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