A method is disclosed. The method includes: obtaining a circuit design including a plurality of 2D cells of a 2D cell library; partitioning the plurality of 2D cells of the circuit design into a first group assigned to a first tier and a second group assigned to a second tier; swapping the 2D cells assigned to the first tier with corresponding 3D cells of a first type 3D cell library respectively; and swapping the 2D cells assigned to the second tier with corresponding 3D cells of a second type 3D cell library respectively; wherein at least one of the obtaining, partitioning, and swapping is performed using a processor. An associated system is also disclosed.