A display panel includes a plurality of data lines and a multiplexer circuit including a first switch set and a second switch set each having a plurality of switches. Each switch of the switch sets has a first end connected to the data lines and a second end. The second ends of a same switch set are connected to each other to form a receiving end connected to a data signal source. The first switch set is turned on alternately by a first clock signal and a second clock signal. The second switch set is turned alternately by a third clock signal and a fourth clock signal. The enabling period of the first clock signal and that of the third clock signal partially overlap and have asynchronous starting times. The enabling period of the second clock signal and that of the fourth clock signal at least partially overlap.