- Patent Title: Semiconductor wafer, and method for polishing semiconductor wafer
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Application No.: US16327067Application Date: 2018-04-06
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Publication No.: US10679842B2Publication Date: 2020-06-09
- Inventor: Taku Yoshida , Hideki Kurita
- Applicant: JX Nippon Mining & Metals Corporation
- Applicant Address: JP Tokyo
- Assignee: JX Nippon Mining & Metals Corporation
- Current Assignee: JX Nippon Mining & Metals Corporation
- Current Assignee Address: JP Tokyo
- Agency: Faegre Drinker Biddle & Reath LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@6849e2fb
- International Application: PCT/JP2018/014679 WO 20180406
- International Announcement: WO2018/198718 WO 20181101
- Main IPC: H01L21/02
- IPC: H01L21/02 ; B24B57/02 ; C30B29/40 ; B24B37/20 ; B24B37/08 ; H01L21/304

Abstract:
The present invention provides: an InP wafer optimized from the viewpoint of small edge roll-off (ERO) and sufficiently high flatness even in the vicinity of a wafer edge; and a method for effectively producing the InP wafer. The InP wafer having a roll-off value (ROA) of from −1.0 μm to 1.0 μm is obtained by using a method including: performing a first stage polishing under a processing pressure of from 10 to 200 g/cm2 for a processing time of from 0.1 to 5 minutes, while supplying a polishing solution containing bromine to at least one side of an InP single crystal substrate that will form the InP wafer; and performing a second stage polishing under a processing pressure of from 200 to 500 g/cm2 for a processing time of from 0.5 to 10 minutes, provided that the processing pressure is higher than that of the first stage polishing by 50 g/cm2 or higher.
Public/Granted literature
- US20190189421A1 SEMICONDUCTOR WAFER, AND METHOD FOR POLISHING SEMICONDUCTOR WAFER Public/Granted day:2019-06-20
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